Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure

ABSTRACT

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of co-pending U.S.patent application Ser. No. 16/049,735 filed on Jul. 30, 2018, which isa divisional application of U.S. patent application Ser. No. 15/460,032filed on Mar. 15, 2017 and issued as U.S. Pat. No. 10,121,742 on Nov. 6,2018, which are expressly incorporated by reference herein, and prioritythereto is hereby claimed.

BACKGROUND OF THE DISCLOSURE

The present invention relates, in general, to electronics, and moreparticularly, to semiconductor packages, structures thereof, and methodsof forming semiconductor packages.

In the past, packaged power semiconductor devices utilized variousmanufacturing techniques to deposit conductive materials on exposedportions of conductive lead frames. In discrete power semiconductordevices, such as discrete field effect transistor (FET) semiconductordevices or diode semiconductor devices, manufacturers have utilizedmatrix lead frames that typically include an array of die attach padseach with a plurality of leads disposed proximate to but isolated fromthe die attach pads. Semiconductor die were attached to the die attachpads and electrically connected to the leads using discrete,stand-alone, or separated connective structures, such as wirebondinterconnects or clips. This sub-assembly was then encapsulated toprovide molded package bodies for each semiconductor die. Next, theencapsulated sub-assembly was placed in an electroplating apparatus andconductive material plated onto exposed surfaces of the conductive leadframes. During the electroplating process, current is passed throughconductive leads, which reduces dissolved metal cations to form a thincoherent metal coating on exposed surfaces of the conductive lead frame.

One problem with this past approach is that in order for current to passthrough the entire conductive lead frame, certain leads from adjoiningsections of the lead frame must be joined together. After theelectroplating process, the individually packaged semiconductor devicesare then separated using a saw process. The saw process separates thejoined leads thereby providing lead faces or flank surfaces withoutelectroplated material. This leaves unwanted exposed lead framematerial, which is typically copper. The exposed copper does not wetwith solder, which produces weaker solder joints and detrimentallyaffects the reliability of assembled electronic components.

In attempt to address this problem, manufacturers have punched holes inthe joined leads, created half-etched regions in the joined leads, orused side grooves in the joined leads to provide some side surface orflank surface coverage of the plated material. Although these approachesproduced lead faces with between about 20% and 60% wettable surfacecoverage for these side or flank surfaces, these approaches cannotprovide up to 100% coverage, and thus have still produced inferiorsolder joints. Also, these approaches have not provided strong enoughsolder joint protection at the assembly board level as required tofulfill stringent automotive specifications, which require 100% wettableflank coverage.

Accordingly, it is desirable to have a method and a structure thatprovides a packaged semiconductor device that improves the wettablesurface coverage for side or flank surfaces of the lead frame. It isalso desirable for the structure and method to be easily incorporatedinto manufacturing flows, and to be cost effective.

BRIEF SUMMARY

The present description includes, among other features, a method ofmanufacturing a packaged semiconductor using a conductive framestructure having a plurality (i.e., at least two) conductive connectivestructures ganged together. The ganged conductive connective structureis used to pass current to conductive components on another conductiveframe structure having exposed conductive flank surfaces to facilitateimproved coverage of the exposed conductive flank surfaces withsolderable material. The method and resulting structure provide, amongother things, a packaged semiconductor device configured to provide upto a 100% wettable flank surfaces. That is, the method and structureprovide exposed side or conductive flank surfaces substantially coveredwith solderable material that facilitates an improved wettable surfacefor attaching to a next level of assembly, such as a printed circuitboard. The method and structure provide for improved reliability byfacilitating stronger solder joints compared to previous approaches. Themethod and structure are suitable for packaged semiconductor devices andother electronic devices having exposed flank or side surfacesconfigured for subsequent deposition of solderable materials, including,but not limited to, power semiconductor devices having flank surfaces ontwo opposing sides of the packaged semiconductor device.

More particularly, in one embodiment, a method for forming packagedsemiconductor devices comprises providing a first conductive framestructure. The method includes coupling a second conductive framestructure to the first conductive frame structure to provide a firstsub-assembly, wherein the second conductive frame structure comprises aplurality of interconnected conductive connective structures. The methodincludes encapsulating the first sub-assembly with an encapsulatinglayer to provide an encapsulated sub-assembly. The method includesremoving joined conductive portions of the first conductive framestructure to form a plurality of conductive flank surfaces disposed onside surfaces of the encapsulated sub-assembly. The method includesforming a conductive layer on the conductive flank surfaces. The methodincludes separating the encapsulated sub-assembly to provide thepackaged semiconductor devices each having portions of the conductiveflank surfaces covered by the conductive layer.

In another embodiment, a method of making packaged electronic devicescomprises providing a first conductive frame structure, which includes afirst sub-structure having a first conductive component, a secondsub-structure having a second conductive component, wherein the firstconductive component is adjoined to the second conductive component toprovide a joined conductive structure connecting the first sub-structureto the second sub-structure, a first electronic die is coupled to thefirst sub-structure, and a second electronic die is coupled to thesecond sub-structure. The method includes providing a second conductiveframe structure, which includes a first conductive connective structure,and a second conductive connective structure, wherein the firstconductive connective structure is physically interconnected to thesecond conductive connective structure, attaching the first conductiveconnective structure to the first electronic die and the firstconductive component and attaching the second conductive connectivestructure to at least the second electronic die to form a firstsub-assembly. The method includes encapsulating portions of the firstsub-assembly with an encapsulating layer to form an encapsulatedsub-assembly, wherein at least portions of the first conductive framestructure are exposed to the outside of the encapsulated sub-assembly.The method includes removing all of the joined conductive structure toform a first conductive component exposed side surface and a secondconductive component exposed side surface. The method includes forming aconductive layer on the exposed surfaces of the first conductive framestructure, on the first conductive component exposed side surface, andon the second conductive component exposed side surface. The methodincludes separating the encapsulated sub-assembly to provide a firstpackaged electronic device having the first conductive component exposedside surface covered by the conductive layer and a second packagedelectronic device having the second conductive component exposed sidesurface covered by the conductive layer.

In a further embodiment, a packaged semiconductor device comprises a dieattach pad, a plurality of leads disposed proximate to the die attachpad, each lead having a lead bottom surface and a lead end surface. Asemiconductor die is connected to the die attach pad and a conductiveclip is attached to the semiconductor die and the plurality of leads,wherein the conductive clip comprises at least one tie bar. A packagebody encapsulates the semiconductor die, the conductive clip, portionsof the plurality of leads, at least a portion of the at least one tiebar portion, and at least a portion of the die pad, wherein each leadend surface is exposed on a side surface of the package body, andwherein an end surface of the at least one tie bar is exposed to theoutside of the package body. A conductive layer is disposed on each leadend surface but not disposed on the end surface of the at least one tiebar.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional and partial perspective view of apackaged semiconductor device in accordance with an embodiment of thepresent invention, where the cross-sectional view is taken alongreference line 1-1 of FIG. 3A;

FIG. 2 illustrates a partial cross-sectional view of a portion of thepackaged semiconductor device of FIG. 1;

FIG. 3A illustrates a top view of the packaged semiconductor device ofFIG. 1 with a portion of the package body illustrated as partiallytransparent;

FIG. 3B illustrates an enlarged partial side view of the packagedsemiconductor device of FIG. 3A;

FIG. 4 illustrates a top view of a conductive frame structure havingelectronic die attached to die attach pads in accordance with anembodiment of the present invention;

FIG. 5 illustrates a top view of a conductive frame structure havinginterconnected conductive connective structures in accordance with anembodiment of the present invention;

FIG. 6 illustrates a top view of the conductive frame structure of FIG.5 disposed overlying the conductive frame structure of FIG. 4 to providea sub-assembly in accordance with an embodiment of the presentinvention;

FIG. 7 illustrates a cross-sectional view of the sub-assembly of FIG. 6taken along reference line 7-7;

FIG. 8 illustrates a cross-sectional view of the sub-assembly of FIG. 6taken along reference line 8-8;

FIG. 9 illustrates a cross-sectional view of the sub-assembly of FIG. 8after further processing in accordance with an embodiment of the presentinvention; and

FIG. 10 illustrates a cross-sectional view of the sub-assembly of FIG. 9after additional processing in accordance with an embodiment of thepresent invention.

For simplicity and clarity of the illustration, elements in the figuresare not necessarily drawn to scale, and the same reference numbers indifferent figures denote the same elements. Additionally, descriptionsand details of well-known steps and elements are omitted for simplicityof the description. As used herein, the term and/or includes any and allcombinations of one or more of the associated listed items. In addition,the terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms comprises, comprising, includes,and/or including, when used in this specification, specify the presenceof stated features, numbers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, numbers, steps, operations, elements, components, and/orgroups thereof. It will be understood that, although the terms first,second, etc. may be used herein to describe various members, elements,regions, layers and/or sections, these members, elements, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one member, element, region, layer and/orsection from another. Thus, for example, a first member, a firstelement, a first region, a first layer and/or a first section discussedbelow could be termed a second member, a second element, a secondregion, a second layer and/or a second section without departing fromthe teachings of the present disclosure. Reference to “one embodiment”or “an embodiment” means that a particular feature, structure orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, appearancesof the phrases “in one embodiment” or “in an embodiment” in variousplaces throughout this specification are not necessarily all referringto the same embodiment, but in some cases it may. Furthermore, theparticular features, structures or characteristics may be combined inany suitable manner, as would be apparent to one of ordinary skill inthe art, in one or more embodiments. Additionally, the term while meansa certain action occurs at least within some portion of a duration ofthe initiating action. The use of word about, approximately orsubstantially means a value of an element is expected to be close to astate value or position. However, as is well known in the art there arealways minor variances preventing values or positions from being exactlystated. Unless specified otherwise, as used herein the word over or onincludes orientations, placements, or relations where the specifiedelements can be in direct or indirect physical contact. It is furtherunderstood that the embodiments illustrated and described hereinaftersuitably may have embodiments and/or may be practiced in the absence ofany element that is not specifically disclosed herein.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional and partial perspective view of apackaged electronic device 10, such as a packaged semiconductor device10 in accordance with a first embodiment, where the cross-sectional viewis taken along reference line 1-1 of FIG. 3A. In accordance with thepresent embodiment, packaged semiconductor device 10 includes a dieattach pad 11, die pad 11, or support pad 11 and leads 12 disposedproximate to, but separated from, die attach pad 11. In one embodiment,an electronic chip 16 or electronic die 16, such as a semiconductordevice 16 or semiconductor die 16 is connected or attached to die attachpad 11 using die attach material 17. In some embodiments, semiconductordevice 16 is a power semiconductor device, such as a power field effecttransistor (FET) structure, a diode structure, or a rectifier structure.It is understood that electronic chip 16 can be other types ofelectronic devices. By way of example, die attach material 17 can be asolder paste, a conductive epoxy, conductive adhesives, conductivefilms, non-conductive epoxy, non-conductive adhesives, non-conductivefilms, or other suitable attach materials as known to those of skill inthe art. In some embodiments, non-conductive refers to electricallyinsulating and it is understood that such materials may still bethermally conductive.

Packaged semiconductor device 10 further includes a conductiveconnective structure 19 attached to a major surface of semiconductordevice 16 and further connected to one or more leads 12. In onepreferred embodiment, conductive connective structure 19 is a conductiveclip style interconnect structure, which is attached to leads 12 asgenerally illustrated in FIG. 3A. In other embodiments, conductiveconnective structure 19 is attached to a single lead 12. In someembodiments, conductive connective structure 19 is mainly composed ofcopper, but other conductive materials can be used as well. Asillustrated in FIGS. 1 and 3A, conductive connective structure 19includes a die attach portion 191 connected to semiconductor device 16using a die attach material 18, which can be a solder paste, aconductive epoxy, conductive adhesives, conductive films, or othersuitable attach materials as known to those of skill in the art.Conductive connective structure 19 further includes a bonding portion192, which extends outward or away from die attach portion 191 at anangle that places bonding portion 192 in an appropriate position forattaching to leads 12 using an attachment layer 23. By way of example,attachment layer 23 can be a solder paste, a conductive epoxy,conductive adhesives, conductive films, or other suitable attachmaterials as known to those of skill in the art. In accordance with thepresent embodiment, conductive connective structure 19 is configured toboth provide an electrical interconnect to leads 12 for passingelectrical signals to and from semiconductor device 16 in finishedpackaged form, and to provide an electrical interconnect forelectroplating purposes while in sub-assembly form during themanufacturing of packaged semiconductor device 10.

Packaged semiconductor device 10 further includes a package body 36 thatcovers or encapsulates conductive connective structure 19, semiconductordie 16, at least portions of leads 12, and at least portions of dieattach pad 11 while, in some embodiments, leaving lower or bottomsurfaces 122 of leads 12, conductive side surfaces 121 (also referred toas conductive flank surfaces 121) of leads 12 exposed to the outside ofpackaged semiconductor device 10 as generally illustrated in FIG. 1. Insome embodiments, package body 36 can be polymer based compositematerial, such as epoxy resin with filler, epoxy acrylate with filler,or polymer with proper filler. Package body 36 comprises anon-conductive and environmentally protective material that protectssemiconductor die 16 from external elements and contaminants. Packagebody 36 may be formed using paste printing, compressive molding,transfer molding, over-molding, liquid encapsulant molding, vacuumlamination, other suitable applicator, or other processes as known tothose of skill in the art. In some embodiments, package body 36 is anepoxy mold compound (“EMC”) and can be formed using transfer orinjection molding techniques.

In accordance with the present embodiment, conductive side surfaces 121or conductive flank surfaces 121 are exposed through side surfaces 360of package body 36, and further covered by a conductive layer 26, suchas a solderable layer 26. By way of example, conductive layer 26comprises tin and preferably is formed in accordance with the presentembodiment using electroplating techniques. In some embodiments,conductive layer 26 is further disposed on lower surfaces 122 of leads12 and on a bottom or lower surface 110 of die attach pad 11 asgenerally illustrated in FIG. 1.

As will be described in more detail later, during the manufacture ofpackaged semiconductor device 10 together with other packagessemiconductor devices in, for example, sub-assembly form, conductiveconnective structure 19 is interconnected or ganged together with otherconductive connective structures (for example, other conductiveconnective structures 19), which according to the present embodimentenables conductive layer 26 to be disposed on all of conductive flanksurfaces 121 of leads 12. More particularly, the interconnectedconductive connective structures 19 enable current to flow through leads12 to facilitate the formation of conductive layer 26 duringelectroplating to provide increased coverage of conductive layer 26compared to previous structures and processes. In accordance with thepresent embodiment, substantially all of conductive flank surfaces 121are covered by conductive layer 26. More particularly, in someembodiments, more than 60% of each conductive flank surface 121 iscovered by conductive layer 26. In some embodiments, more than about 75%of each conductive flank surface 121 is covered by conductive layer 26.In preferred embodiments, approximately 100% or substantially all ofeach conductive flank surface 121 is covered by conductive layer 26.

FIG. 2 illustrates a partial cross-sectional view of a portion ofpackaged semiconductor device 10. With reference to FIG. 2, a portion ofpackaged semiconductor 10 is illustrated attached to a next level ofassembly 200, such as a printed circuit board 200 having a conductivetrace 201 disposed proximate to a first surface 203. In accordance withthe present embodiment, conductive flank surface 121 of lead 12 issubstantially covered by conductive layer 26, which facilitatesapproximately a 100% wettable flank for solder attach material 24. Inaccordance with the present embodiment, this improves the solder jointstrength and the reliability of the assembled component compared toprevious methods that are incapable of providing greater than 60%solderable material coverage on the flank surfaces.

FIG. 3A illustrates a top view of packaged semiconductor device 10 witha portion of package body 36 illustrated as partially transparent toview internal portions of the device. In accordance with the presentembodiment, conductive connective structure 19 further includes one ormore tie bars 194 extending outward from, for example, die attachportion 191 of conductive connective structure 19 to side surfaces 361and 362 of package body 36. In one preferred embodiment, conductiveconnective structure 19 comprises at least two tie bars 194 on opposingsides 196 and 197 respectively of conductive connective structure 19 asgenerally illustrated in FIG. 3A. In one embodiment, tie bars 194 areconfigured to interconnect, physically connect, or gang togetherconductive connective structure 19 to other conductive connectivestructures (for example, other conductive connective structures 19) inaccordance with the present embodiment. In one embodiment, a conductiveconnective structure 116, such as a conductive wire bond, electricallyconnects another pad portion on semiconductor device 16 to a lead 112 asgenerally illustrated in FIG. 3A.

FIG. 3B is an enlarged partial side view of packaged semiconductordevice 10 illustrating a portion of side surface 362 of package body 36where a distal end surface 195 of tie bar 194 is exposed through packagebody 36. In accordance with the present embodiment, distal end surface195 is absent conductive material 26 because tie bars 194 are separatedor singulated after conductive layer 26 is formed.

Turning now to FIGS. 4-10, a method for forming packaged electronicdevices or packaged semiconductor devices including packagesemiconductor device 10 will be described. FIG. 4 illustrates a top viewof a conductive frame structure 40 having electronic die 16, such as asemiconductor die, attached to die attach pads 11 in accordance with afirst embodiment. In an early step of manufacture, conductive framestructure 40 is provided having a plurality of sub-structures 41, 42,43, and 44 or sub-frame structures 41, 42, 43, and 44. In oneembodiment, conductive frame structure 40 can be provided as an N×Marray of sub-structures including a 2×2 array as generally illustratedin FIG. 4. In some embodiments, each sub-structure can include a dieattach pad 11 attached to a conductive frame 51 or frame 51, which isspaced apart and surrounds die attach pad 11. In some embodiments, eachframe 51 can have a square shape and die attach pad 11 can be attachedto frame 51 with one or more tie bars 53 and/or lead portions 511. Leads12 are disposed spaced apart but proximate to die attach pads 11 and canbe attached at ends distal to die attach pads 11 to frame 51, asgenerally illustrated in FIG. 4.

In some embodiments, conductive frame structure 40 includes a mainportion 48 or a tap portion 48 disposed on one side of conductive framestructure 40, which may further include one or more holes 49. In someembodiments, leads 12 corresponding to a die attach pad 11 within asub-structure are disposed only one side of die attach pad 11. In otherembodiments, leads 12 can disposed on more than one side of die attachpad 11. As generally illustrated in FIG. 4, leads 12 of sub-structure 41have distal ends joined to distal ends of lead portions 511 extendingoutward from die attach pad 11 in sub-structure 42. In some embodiments,where these distal ends are joined is referred to as joined conductiveportions 56. In some embodiments, each joined conductive portion 56includes at least a portion of frame 51 interposed between the distalends of leads 12 and lead portions 511. It is understood that joinedconductive portions 56 can also include portions adjoining leads 12 thatare directly attached to a die attach pad 11 in an adjacentsub-structure, can include portions adjoining leads 12 from adjacentsub-structures, and can include combinations thereof. In general, joinedconductive portions 56 are those portions of conductive frame structure40 that will be separated, singulated, or removed in subsequentprocessing thereby exposing conductive flank surfaces, conductive sidessurfaces, or conductive distal end surfaces of the leads, lead portions,die attach pads, or conductive portions exposed after the separationprocess.

In accordance with the present embodiment, frame structure 40 comprisesa conductive material. In one embodiment, conductive frame structure 40is mainly composed of copper and is approximately 100 μm through 508 μmin thickness. In other embodiments, frame structure 40 can be mainlycomposed of Fe—Ni (e.g., Alloy 42) or any other metal material(s) asknown to those of skill in the art. Conductive frame structure 40 can beformed or manufactured using masking and etch techniques, stampingtechniques, bending or forming techniques, plating techniques,deposition techniques, machining, and/or combinations thereof. As statedbefore, each electronic die 16, such as semiconductor die 16, can beconnected to die attach pads 11 using die attach material 17, asgenerally illustrated in FIG. 1. In some embodiments, a pad portion ofeach electronic die 16 is electrically connected to a lead 12 with aconductive connective structure 116, such as a wire bond structure. Itis understood that conductive connective structures 116 can be formed ata later step of fabrication, such as after conductive frame structure 60is attached.

FIG. 5 illustrates a top view of a conductive frame structure 60 havinginterconnected conductive connective structures 19 in accordance withone embodiment, which can be provided in a step of manufacture. Inaccordance with the present embodiment, conductive frame structure 60can be provided as N×M array similar to conductive frame structure 40including a 2×2 array as generally illustrated in FIG. 5. By way ofexample, conductive frame structure 60 can be configured to include aplurality of sub-structures 61, 62, 63, and 64 or sub-frame structures61, 62, 63, and 64. In accordance with the present embodiment,conductive connective structures 19 in each of sub-structures 61, 62,63, and 64 are physically and electrically interconnected or gangedtogether so that the interconnected conductive connective structures 19can be used to provide current to conductive components in conductiveframe structure 40 during a subsequent electroplating process. In someembodiments, each of the conductive connective structures 19 isinterconnected to a conductive frame 71 or frame 71 that is spaced apartfrom and surrounds each conductive connective structure 19 as generallyillustrated in FIG. 5. In some embodiments, tie bars 194 are used tointerconnect the conductive connective structures 19 together with frame71. In one preferred embodiment, each conductive connective structure 19comprises at least two tie bars 194 on opposing sides 196 and 197respectively of conductive connective structure 19 as generallyillustrated in FIG. 5. In one preferred embodiment, tie bars 194 arepositioned within conductive frame structure 60 to be perpendicular toleads 12 in conductive frame structure 40. Stated another way, tie bars194 are positioned so that when conductive frame structure 60 isattached to conductive frame 40 tie bars 194 reside on sides of eachsub-assembly that are absent conductive flank surfaces that will besubsequently electroplated. This configuration prevents tie bars 194from being prematurely singulated when joined conductive portions 56 areremoved.

In some embodiments, conductive frame structure 60 includes a mainportion 68 or tap portion 68 disposed on one side of conductive framestructure 60, which may further include one or more holes 69. As will bedescribed in more detail later, main portion 68 is configured tophysically contact or electrically connect to main portion 48 ofconductive frame structure 40 to allow current to flow through bothconductive frame structure 40 and conductive frame structure 60including conductive interconnects structures 19 during anelectroplating process.

In accordance with the present embodiment, frame structure 60 comprisesa conductive material. In one embodiment, conductive frame structure 60is mainly composed of copper and is approximately 100 μm through 508 μmin thickness. In other embodiments, frame structure 60 can be mainlycomposed of Fe—Ni (e.g., Alloy 42) or any other metal material(s) asknown to those of skill in the art. Conductive frame structure 60 can beformed or manufactured using masking and etch techniques, stampingtechniques, bending or forming techniques, plating techniques,deposition techniques, machining, and/or combinations thereof.

FIG. 6 illustrates a top view of conductive frame structure 60 disposedoverlying conductive frame structure of 40 to provide a sub-assembly 80in accordance with an embodiment. In one embodiment, in an additionalstep, conductive frame structure 60 and conductive frame 40 areconnected together, including, for example, attached together byattaching conductive connective structures 19 to semiconductor die 16and to leads 12. As described previously, conductive connectivestructures 19 each can be attached to semiconductor die 16 using a dieattach material 18 (illustrated in FIG. 1), which can be a solder paste,a conductive epoxy, conductive adhesives, conductive films, or othersuitable attach materials as known to those of skill in the art. Inaddition, conductive connective structures 19 each can be attached toleads 12 using an attachment layer 23 (illustrated in FIG. 1), which canbe a solder paste, a conductive epoxy, conductive adhesives, conductivefilms, or other suitable attach materials as known to those of skill inthe art. In some embodiments, an additional attachment layer 418(illustrated in FIG. 7) can be used to attach other portions ofconductive frame structure 60 to conductive frame 40 including, forexample, main portion 68 to main portion 48 to physically connect thesetwo portions together. The additional attachment layer 418 (illustratedin FIG. 7) can be materials similar to die attach material 18. At thisstep, a sub-assembly 80 is provided in accordance with the presentembodiment. Reference is also made in FIG. 6 to portions 401 the will besubsequently removed in accordance with the present, which is furtherdescribed in conjunction with FIG. 10.

FIG. 7 illustrates a cross-sectional view of the sub-assembly 80 takenalong reference line 7-7 of FIG. 6, and FIG. 8 illustrates across-sectional view of sub-assembly 80 taken along reference line 8-8of FIG. 6. As illustrated in FIG. 7 main portion 68 of conductive framestructure 60 has been brought into physical contact with main portion 48of conductive frame structure 40 through, for example, attachment layer418. In accordance with the present embodiment, this contact can be usedto later connect the sub-assembly to a belt finger portion of anelectroplating apparatus, which suspends the sub-assembly within aplating solution. In accordance with the present embodiment, conductiveconnective structures 19 are interconnected together or ganged togetherby tie bars 194 and frame 71 and further interconnected to main portion68. Further, this structure facilitates the passage of current to leads12 during the electroplating process to form conductive layer 26 on theconductive flank surfaces 121 (illustrated as dashed lines) of leads 12.

FIG. 9 illustrates a cross-sectional view of sub-assembly 80 of FIG. 8after further processing. In one embodiment, an encapsulating step isused to form one or more encapsulating package bodies 36 covering atleast portions of sub-assembly 80 to provide an encapsulatedsub-assembly 90. In some embodiments, package bodies 36 can be polymerbased composite material, such as epoxy resin with filler, epoxyacrylate with filler, or polymer with proper filler. Package bodies 36comprise a non-conductive and environmentally protective material thatprotects semiconductor dies 16 from external elements and contaminants.Package bodies 36 may be formed using paste printing, compressivemolding, transfer molding, over-molding, liquid encapsulant molding,vacuum lamination, other suitable applicator, or other processes asknown to those of skill in the art. In some embodiments, package bodies36 are molded structures comprising is an epoxy mold compound (“EMC”)and can be formed using transfer or injection molding techniques.

FIG. 10 illustrates a cross-sectional view of the encapsulatedsub-assembly 90 after additional processing in accordance with thepresent embodiment. In accordance with the present embodiment, portions(e.g., portions 401) of encapsulated sub-assembly 90 are removedincluding joined conductive portions 56 from conductive frame structure40. In one preferred embodiment, joined conductive portions 56 areremoved in their entirety thereby completely exposing the end surfaces(i.e., conductive flank surfaces 121) of leads 12 and lead portions 511.In some embodiments, a partial sawing process is used to remove portionsof conductive frame structure 40 including joined conductive portions56. In some embodiments, a portion of encapsulating layer 360 is removedas well. Other processes can be used to remove portions 401 including,for example, masking and etching techniques, ablation techniques, lasertechniques, and other techniques as known to those skilled in the art.

In a subsequent step, conductive layer 26 is disposed along exposedsurfaces of conductive frame structure 40 including, for example,exposed portions of die attach pads 11, leads 12, and lead portions 511.In one preferred embodiment, encapsulated sub-assembly is placed into aelectroplating bath or solution and current passed through conductiveframe structure 40 and conductive frame structure 60 to electroplateconductive layer 26 onto the exposed surfaces of conductive framestructure 40. In accordance with the present embodiment, interconnectedconductive connective structures 19 are configured to facilitate anelectrical connection to leads 12 thereby electroplating conductivelayer 26 onto exposed conductive flank surfaces 121 of leads 12, whichprovides up to approximately 100% coverage of these surfaces compared toprior processes and structure that provide less than 60% coverage.Conductive layer 26 can be a solderable material, such as tin basedsolder or other solderable materials as known to those of skill in theart. In one embodiment, conductive layer 26 can be a matte tin materialhaving a thickness in range from approximately 300 to approximately 800micro inches (approximately 7.6 microns to approximately 23.0 microns).In one embodiment, a belt finger is attached to main portions 48 and 68of encapsulated sub-assembly 90 for placement into the electroplatingbath or solution.

In some embodiments, after conductive layer 26 is formed, encapsulatedsub-assembly 90 is singulated or separated along, for example,separation regions 403 to provide a plurality of packaged semiconductordevices, such as packaged semiconductor device 10. In some embodiments,a sawing process is used to singulate encapsulated sub-assembly 90, butother separation processes can be used as known to those of skill in theart.

In some embodiments, one or more of die attach pad 11, leads 12,conductive connective structure 19, and tie bars 194, frame 51, tie bars53, lead portions 511, joined conductive portions 56, main portion 48,tie bars 194, frame 71, main portion 68, and/or portions thereof arenon-limiting examples of conductive components.

In view of all of the above, it is evident that a novel method formaking packaged semiconductor devices with improved coverage ofconductive flank surfaces with a solderable material and structure havebeen disclosed. Included, among other features, are a conductive framestructure having interconnected conductive connective structures thatare connected to lead structures in a second conductive frame structure.The conductive frame structure facilities electrical connection toconductive components, such as leads, thereby providing the improvedsolderable material coverage on the conductive flank surfaces. Themethod and structure provide up to 100% wettable flank coverage when thepackaged semiconductor devices are attached to a next level of assembly,such as a printed circuit board. This provides stronger solder jointsand improves reliability compared to previous structures and methods.The method and structure provide a cost effective solution to improvingwettable flank coverage and are compatible with existing assemblymethod.

While the subject matter of the invention is described with specificpreferred embodiments and example embodiments, the foregoing drawingsand descriptions thereof depict only typical embodiments of the subjectmatter, and are not therefore to be considered limiting of its scope. Itis evident that many alternatives and variations will be apparent tothose skilled in the art.

As the claims hereinafter reflect, inventive aspects may lie in lessthan all features of a single foregoing disclosed embodiment. Thus, thehereinafter expressed claims are hereby expressly incorporated into thisDetailed Description of the Drawings, with each claim standing on itsown as a separate embodiment of the invention. Furthermore, while someembodiments described herein include some but not other featuresincluded in other embodiments, combinations of features of differentembodiments are meant to be within the scope of the invention and meantto form different embodiments as would be understood by those skilled inthe art.

What is claimed is:
 1. A method of forming packaged semiconductordevices, comprising: providing a first conductive frame having joinedconductive portions; attaching semiconductor components to the firstconductive frame; providing a second conductive frame comprisinginterconnected conductive clips; attaching the second conductive frameto the first conductive frame to provide a first sub-assembly, whereinthe interconnected conductive clips are coupled to the first conductiveframe; encapsulating the first sub-assembly with an encapsulant toprovide an encapsulated sub-assembly; and separating the encapsulatedsub-assembly to provide the packaged semiconductor devices, wherein thestep of separating disconnects the interconnected conductive clips fromthe second conductive frame.
 2. The method of claim 1, furthercomprising: removing the joined conductive portions of the firstconductive frame to form conductive flank surfaces disposed on sidesurfaces of the encapsulated sub-assembly; and forming a conductivelayer onto the conductive flank surfaces after the step of removing thejoined conductive portions, wherein: the step of separating comprisesproviding each of the packaged semiconductor devices having portions ofthe conductive flank surfaces covered by the conductive layer.
 3. Themethod of claim 2, wherein: forming the conductive layer comprises:electroplating the conductive layer onto the conductive flank surfacesusing the interconnected conductive clips to pass current throughportions of the first conductive frame.
 4. The method of claim 2,wherein: providing the first conductive frame comprises providing: afirst die pad; a second die pad spaced apart from the first die pad; afirst lead disposed proximate to the first die pad; and a second leaddisposed proximate to the second die pad, wherein the first lead isadjoined to one of the second lead or the second die pad to provide oneof the joined conductive portions; a first one of the semiconductorcomponents attached to the first die pad; and a second one of thesemiconductor components attached to the second die pad; attaching thesecond conductive frame to the first conductive frame comprises:attaching a first one of the conductive clips to the first one of thesemiconductor components and the first lead; and attaching a second oneof the conductive clips to the second one of the semiconductorcomponents and the second lead; encapsulating comprises leaving at leastportions of the first conductive frame exposed from the encapsulatedsub-assembly; and removing comprises removing the one of the joinedconductive portions to expose a flank surface of the first lead.
 5. Themethod of claim 4, wherein: providing the first conductive framecomprises providing the first lead physically connected to the seconddie pad within the first conductive frame such that the one joinedconductive portion is interposed between the first lead and the seconddie pad.
 6. The method of claim 4, wherein: forming the conductive layercomprises: forming the conductive layer on bottom surfaces of the firstdie pad, the second die pad, the first lead, and the second lead.
 7. Themethod of claim 2, wherein: separating comprises providing the packagedsemiconductor devices each having a distal end portion of the secondconductive frame structure exposed to the outside of the encapsulatinglayer, and wherein the distal end portion is absent the conductivelayer.
 8. The method of claim 2, wherein: removing the joined conductiveportions comprises partially sawing into the encapsulated sub-assemblyto completely remove the joined conductive portions.
 9. The method ofclaim 2, wherein: forming the conductive layer comprises forming asolderable material covering approximately 100% of the conductive flanksurfaces.
 10. The method of claim 1, wherein: attaching the secondconductive frame to the first conductive frame comprises attaching eachof the interconnected conductive clips to a respective semiconductorcomponent and to a respective part of the first conductive frame.
 11. Amethod of forming packaged semiconductor devices, comprising: providinga first conductive frame; attaching semiconductor components to thefirst conductive frame; providing a second conductive frame comprising afirst clip interconnected to a second clip; attaching the secondconductive frame to the first conductive frame to provide a firstsub-assembly; encapsulating the first sub-assembly with an encapsulantto provide an encapsulated sub-assembly; and separating the encapsulatedsub-assembly to provide the packaged semiconductor devices, wherein thestep of separating disconnects the first clip from the second clip. 12.The method of claim 11, wherein: providing the first conductive framecomprises providing joined conductive portions; and the method furthercomprises: removing the joined conductive portions of the firstconductive frame to form conductive flank surfaces disposed on sidesurfaces of the encapsulated sub-assembly; and forming a conductivelayer over the conductive flank surfaces after the step of removing thejoined conductive portions.
 13. The method of claim 12, whereinproviding the joined conductive portions comprises providing a firstlead connected to a first die pad.
 14. The method of claim 11, wherein:providing the second conductive frame comprises: providing the firstclip physically interconnected to a first part of the second conductiveframe with a first tie bar; and providing the second clip physicallyinterconnected to second part of the second conductive frame with asecond tie bar.
 15. The method of claim 11, wherein attaching the secondconductive frame comprises: attaching the first clip to the firstconductive fame.
 16. The method of claim 15, wherein attaching the firstclip comprises: attaching the first clip to a first semiconductorcomponent.
 17. An encapsulated sub-assembly of semiconductor components,comprising: a first sub-assembly comprising: a first conductive framehaving leads; semiconductor components attached to the first conductiveframe; and a second conductive frame comprising conductive clipsinterconnected with tie bars, each conductive clip comprising a bondingportion connected to at least two leads; and a package body structurecomprising an encapsulating layer covering at least portions of thefirst sub-assembly.
 18. The encapsulated sub-assembly of claim 17,wherein: the leads comprise conductive flank surfaces exposed from sidesurfaces of the encapsulating layer; and the encapsulated sub-assemblyfurther comprises a conductive layer disposed at least adjacent to theconductive flank surfaces, wherein
 19. The encapsulated sub-assembly ofclaim 17, wherein: each conductive clip further comprises a die attachportion attached to one of the semiconductor components.
 20. Theencapsulated sub-assembly of claim 19, wherein: the tie bars areattached to the die attach portion of each conducive clip and the secondconductive fame.